L9659 datasheet(29/51 Pages) STMICROELECTRONICS

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L9659

Functional description

Doc ID 022048 Rev 2

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equation shown in the parametric table. The L9659 is also capable of improving the

tolerance at resistances below 3.5 Ohms by removing the offset of the differential

comparator. This method works taking the single ended analog output results for a channel

(VAOUT with AMC bit=0) and subtracting the internal comparator offset measurement of

VAOUT_CAL (VAOUT with AMC bit=1). The summary of the equation for this is as follows:

AOUT_CAL = (VAOUT – VAOUT_CAL)/VDD

AOUT_CAL typical = 0.08 x RSQUIB

High squib resistance diagnostics

During a high squib resistance diagnostic, VRCM and ISINK are switched ON and

connected to SQHx and SQLx on the selected channel. Current flowing on SQHx will be

measured and compared to IHR threshold to identify if resistance is above or below

RSQHZ. The results will be reported in the next SPI message. Once the command is issued

the state of the squib resistance will be valid after THSR captured on the next falling edge of

CS_D. The voltage source for this test will be VBIAS which is based on the VDD supply.

A way to reduce the time required until valid results are available is to perform a leakage

diagnostics prior to this test. The leakage diagnostics will bias the voltage on the squibs to

around 3.5V, which is the same bias voltage required for the high squib resistance

diagnostic. By following running this sequence of diagnostics will reduce the test time to

from 1.5ms to 200µs.

High and low side FET diagnostics

Prior to either the HS or LS FET diagnostics being run it is required to have the VRCM

switched ON. Running the leakage diagnostics with the appropriate delay time prior to either

the HS or LS FET diagnostics can do this. When the FET diagnostic command is issued the

flags will initially be cleared. If the VRMC is not active or some leakage is present then the

MOS will not be turned ON, the test will be aborted and Fault Present (FP) bit will be set.

The FEN function must be inactive to run test. The test will not start if FEN function is active

on channel under test and it will result in the Fault Present (FP) bit to set.

If no leakage is present and FEN function is inactive, the MOS (High side or Low Side) is

turned ON. The L9659 will monitor the current sink or sourced by VRCM. If the MOS is

working properly, this current will exceed ISTB (HS test) or ISTG (LS test) and the L9659 will

turn off the driver under test within the specified time TSHUTOFF. If the current does not

exceed ISTB or ISTG then the test will be terminated and the MOS will be switched off by

the L9659 within TFETTIMEOUT. During the TFETTIMEOUT period the FET Timeout bit will be

set (FT=1) and will be cleared at the expiration of the timer.

The results must be compared with the leakage diagnostic results to distinguish between a

real leakage/short versus a FET fault. For high side FET diagnostics if no faults were

indicated in the preceding leakage diagnostics then a normal result would be STB=1;STG=0

(with FT=0;FP=0). If the returned results for the high side FET test is not STB=1;STG=0

(with FT=0;FP=0) then either the FET is not functional, a short occurred during the test, or

there is a missing VRESx connection for that channel. For low side FET diagnostics if no

faults were indicated in the preceding leakage diagnostics then a normal result would be

STB=0;STG=1 (with FT=0;FP=0). If the returned results for the low side FET test is not

STB=0;STG=1 (with FT=0;FP=0) then either the FET is not functional, a short occurred

during the test, or there is a missing GNDx connection for that channel. If the test is in

progress then a bit (FT) is used in the response to indicate this status.

Once the command is issued, output of comparators will be latched.

L9659 Datasheet(PDF) 29 Page - STMicroelectronics

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