SPC56EL70L3 datasheet(95/128 Pages) STMICROELECTRONICS

95 / 128 page

DocID023953 Rev 5

95/128

SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5

Electrical characteristics

127

Equation 4

generates a constraint for external network design, in particular on resistive path.

Internal switch resistances (RSW and RAD) can be neglected with respect to external

resistances.

Figure 9. Input Equivalent Circuit

A second aspect involving the capacitance network shall be considered. Assuming the three

capacitances CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the

equivalent circuit reported in Figure 9): A charge sharing phenomenon is installed when the

sampling phase is started (A/D switch close).

Figure 10. Transient Behavior during Sampling Phase

In particular two different transient periods can be distinguished:

A first and quick charge transfer from the internal capacitance CP1 and CP2 to the

sampling capacitance CS occurs (CS is supposed initially completely discharged):

---------------------



---LSB



RSW1

CP2

VREF

Sampling

Source

Filter

Current Limiter

EXTERNAL CIRCUIT

INTERNAL CIRCUIT SCHEME

RS Source Impedance

RF Filter Resistance

CF Filter Capacitance

RL Current Limiter Resistance

RSW1 Channel Selection Switch Impedance

RADSampling Switch Impedance

CP Pin Capacitance (two contributions, CP1 and CP2)

CS Sampling Capacitance

CP1

RAD

Channel

Selection

VA1

VA2

VCS

Voltage Transient on CS

V <0.5 LSB





1 < (RSW + RAD) CS << TS



2 = RL (CS + CP1 + CP2)

SPC56EL70L3 Datasheet(PDF) 95 Page - STMicroelectronics

SPC56EL70L3 Datasheet(HTML) 95 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL