ST10F296 datasheet(315/346 Pages) STMICROELECTRONICS

315 / 346 page

Obsolete

Product(s)

- Obsolete

Product(s)

ST10F296E

Electrical characteristics

315/346

24.8.6

Oscillator watchdog (OWD)

An on-chip watchdog oscillator is implemented in the ST10F296E. This feature is used for

safety reasons with an external crystal oscillator (available only when using direct drive

mode with or without prescaler, so the PLL is not used to generate the CPU clock

multiplying the frequency of the external crystal oscillator). The watchdog oscillator operates

as follows:

The reset default configuration enables the watchdog oscillator. It can be disabled by setting

the OWDDIS bit (bit 4) of the SYSCON register.

When the OWD is enabled, the PLL runs at its free-running frequency and it increments the

watchdog counter. At each transition of the external clock, the watchdog counter is cleared.

If an external clock failure occurs, the watchdog counter overflows (after 16 PLL clock

cycles).

When overflow occurs, the CPU clock signal is switched to the PLL free-running clock signal

and the oscillator watchdog interrupt request is flagged. The CPU clock does not switch

back to the external clock even if a valid external clock exits on the XTAL1 pin. Only a

hardware reset (or bidirectional software/watchdog reset) can switch the CPU clock source

back to direct clock input.

When the OWD is disabled, the CPU clock is always the external oscillator clock (in direct

drive or prescaler operation) and the PLL is switched off to decrease consumption supply

current.

24.8.7

Phase-locked loop (PLL)

For all combinations of pins P0.15-13 (P0H.7-5) other than 011, during reset, the on-chip

PLL is enabled and it provides the CPU clock (see Table 168). The PLL multiplies the input

frequency by the factor ‘F’ which is selected via the combination of pins P0.15-13 (fCPU =

fXTAL x F). With every F’th transition of fXTAL, the PLL circuit synchronizes the CPU clock to

the input clock. This synchronization is done smoothly, so the CPU clock frequency does not

change abruptly.

Due to this synchronization with the input clock, the frequency of fCPU is constantly adjusted

so it is locked to fXTAL. The resulting slight variation causes a jitter of fCPU which also effects

the duration of individual TCLs.

The timings listed in this section that refer to TCLs must be calculated using the minimum

possible TCL under the respective circumstances.

The minimum value for TCL depends on the jitter of the PLL. The PLL tunes the fCPU to

keep it locked on fXTAL. The relative deviation of TCL is the maximum when it is referred to

one TCL period.

This is especially important for bus cycles using wait states and for the operation of timers, serial

interfaces, etc. For all slower operations and longer periods (such as, pulse train generation or

measurement, lower baud rates, etc) the deviation caused by the PLL jitter is negligible. Refer to

Section 24.8.9: PLL jitter for more details.

Obsolete

Product(s)

- Obsolete

Product(s)

ST10F296 Datasheet(PDF) 315 Page - STMicroelectronics

ST10F296 Datasheet(HTML) 315 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL