ST10F296 datasheet(318/346 Pages) STMICROELECTRONICS

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Electrical characteristics

ST10F296E

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The jitter in the PLL loop can be modeled as being dominated by the i1/f2 noise for N smaller

than a ‘certain’ value that depends on the PLL output frequency and on the bandwidth

characteristics of the program loop. Above this ‘certain’ value, the jitter becomes dominated

by the i1/f3 noise component. For N greater than a second value of N, the jitter does not

increase with a longer time interval due to an apparent saturation effect (the jitter is stable,

thereby increasing the number of clock periods, N). The PLL loop acts as a high pass filter

for any noise in the loop, with a cutoff frequency equal to the bandwidth of the PLL. The

saturation value corresponds to self referred long term jitter of the PLL. Figure 105 shows

the maximum jitter trend versus the number of clock periods N (for some typical CPU

frequencies). The curves represent the worst case situations, as they are computed taking

into account all temperature ranges, power supplies and process variations. ‘Real’ jitter is

always measured well below the given worst case value.

Noise in supply and substrate

Digital supply noise adds determining elements to PLL output jitter, independent of the

multiplication factor. Its effect is strongly reduced thanks to the particular care taken when

integrating and implementing the PLL module inside the device. In addition, the contribution

of digital noise to global jitter is widely taken into account in the curves provided in

Figure 105.

Figure 105. ST10F296E PLL jitter

N (CPU clock periods)

200

400

±5

±1

800

600

1000

1200

1400

64 MHz

±2

±3

±4

24 MHz

40 MHz

32 MHz

16 MHz

TJIT

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ST10F296 Datasheet(PDF) 318 Page - STMicroelectronics

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