ST10F296 datasheet(321/346 Pages) STMICROELECTRONICS

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Electrical characteristics

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The input frequency range is 4-12 MHz when using an external clock source. With an

external clock source, 64 MHz can be applied only when Direct Drive mode is selected. In

this case, the oscillator amplifier is bypassed so it does not limit the input frequency.

Figure 107. External clock drive XTAL1

When direct drive is selected, an external clock source can be used to drive XTAL1. The maximum

frequency of the external clock source depends on the duty cycle. When 64 MHz is used, 50 % duty cycle

is granted (low phase = high phase = 7.8 ns). When 32 MHz is used, a 25 % duty cycle can be accepted

(minimum, high or low phase = 7.8 ns).

24.8.15

Memory cycle variables

Table 174 describes how three variables derived from the BUSCONx registers are

computed. These variables represent special characteristics of the programmed memory

cycle.

Table 173.

External clock drive timing

Symbol

Parameter

Direct drive

fCPU = fXTAL

Direct drive with

prescaler

fCPU = fXTAL/2

PLL use

fCPU = fXTAL x F

Unit

Min

Max

Min

Max

Min

Max

tOSC (SR)

XTAL1 period(1)

The minimum value for the XTAL1 signal period is considered as the theoretical minimum. The real

minimum value depends on the duty cycle of the input clock signal.

15.625

83.3

250

83.3

250

t1 (SR)

High time(2)

The input clock signal must reach the defined levels VIL2 and VIH2.

t2 (SR)

Low time(2)

t3 (SR)

Rise time(2)

-2

t4 (SR)

Fall time(2)

VIL2

tOSC

VIH2

Table 174.

Memory cycle variables

Symbol

Description

Values

ALE extension

TCL x [ALECTL]

Memory cycle time wait states

2TCL x (15 - [MCTC])

Memory tri-state time

2TCL x (1 - [MTTC])

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