ST10F296 datasheet(319/346 Pages) STMICROELECTRONICS

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Electrical characteristics

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24.8.12

PLL lock/unlock

If the PLL is unlocked for any reason during normal operation, an interrupt request to the

CPU is generated and the reference clock (oscillator) is automatically disconnected from the

PLL input. In this way, the PLL goes into free-running mode, providing the system with a

backup clock signal (free running frequency Ffree). This feature allows the device to recover

from a crystal failure occurrence without risking entering an undefined configuration. The

system is provided with a clock allowing the execution of the PLL unlock interrupt routine in

a safe mode.

The path between the reference clock and PLL input can be restored only by a hardware

reset or by a bidirectional software or watchdog reset event that forces the RSTIN pin low.

Note:

The external RC circuit on the RSTIN pin must be the right size to extend the duration of the

low pulse that locks the PLL before the level at the RSTIN pin is recognized as being high. A

bidirectional reset internally drives the RSTIN pin low for 1024 TCL (which is not sufficient to

lock the PLL when starting from free-running mode).

Conditions: VDD = 5 V ±10 %, TA = -40/125

oC.

24.8.13

Main oscillator specifications

Conditions: VDD = 5 V ±10 %, TA = -40/125 °C

Table 170.

PLL lock/unlock timing

Symbol

Parameter

Conditions

Value

Unit

Min

Max

TPSUP

PLL start-up time(1)

Not 100% tested, guaranteed by design characterization.

Stable VDD and reference clock

300

µs

TLOCK

PLL lock-in time

Stable VDD and reference clock,

starting from free-running mode

-250

TJIT

Single period jitter(1)

(cycle to cycle = 2 TCL)

6 sigma time period variation

(peak to peak)

-500

+500

Ffree

PLL free running frequency

Multiplication factors: 3, 4

Multiplication factors: 5, 8, 10, 16

250

500

2000

4000

kHz

Table 171.

Main oscillator specifications

Symbol

Parameter

Conditions

Value

Unit

Min

Typ

Max

Oscillator transconductance

mA/V

VOSC

Oscillation amplitude(1)

Not 100% tested, guaranteed by design characterization

Peak to peak

VDD -0.4

VAV

Oscillation voltage level(1)

Sine wave middle

VDD/2 - 0.25

tSTUP

Oscillator start-up time(1)

Stable VDD - crystal

Stable VDD, resonator

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