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ST10F296 Datasheet(PDF) 320 Page - STMicroelectronics |
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ST10F296 Datasheet(HTML) 320 Page - STMicroelectronics |
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320 / 346 page  Obsolete Product(s) - Obsolete Product(s) Electrical characteristics ST10F296E 320/346 Figure 106. ST10F296ECrystal oscillator and resonator connection diagram The given values of CA do not include the stray capacitance of the package or of the printed circuit board. The negative resistance values are calculated assuming an additional 5 pF to the values in Table 172. The crystal shunt capacitance (C0), the package, and the stray capacitance between XTAL1 and XTAL2 pins is globally assumed to be 4 pF. The external resistance between XTAL1 and XTAL2 does not have to be taken into account, since it is already present on the silicon. 24.8.14 External clock drive XTAL1 When direct drive configuration is selected during reset, it is possible to drive the CPU clock directly from the XTAL1 pin, without any particular restrictions on the maximum frequency, since the on-chip oscillator amplifier is bypassed. The speed limit is imposed by internal logic that targets a maximum CPU frequency of 64 MHz. In all other clock configurations (direct drive with prescaler or PLL use) the on-chip oscillator amplifier is not bypassed, so it determines the input clock speed limit. In this case, an external clock source can be used, but it is limited in the range of frequencies defined for the use of crystal and resonator (see Table 168 on page 313). External clock drive timing conditions: VDD = 5 V ±10 %, VSS = 0 V, TA = -40 to 125 °C. Table 172. Negative resistance (absolute min value @125 °C/VDD = 4.5 V) CA (pF) 12 15 18 22 27 33 39 47 4 MHz 460 Ω 550 Ω 675 Ω 800 Ω 840 Ω 1000 Ω 1180 Ω 1200 Ω 8 MHz 380 Ω 460 Ω 540 Ω 640 Ω 580 Ω -- - 12 MHz 370 Ω 420 Ω 360 Ω -- -- - CA CA Crystal Resonator ST10F296E ST10F296E Obsolete Product(s) - Obsolete Product(s) |
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