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ST10F296 Datasheet(PDF) 323 Page - STMicroelectronics |
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ST10F296 Datasheet(HTML) 323 Page - STMicroelectronics |
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323 / 346 page  Obsolete Product(s) - Obsolete Product(s) ST10F296E Electrical characteristics 323/346 t19 (SR) Data float after RD(1) - 16.5 + tF - 2TCL - 8.5 + tF ns t22 (CC) Data valid to WR 10 + tC - 2TCL - 15 + tC - t23 (CC) Data hold after WR 4 + tF 2TCL - 8.5 + tF t25 (CC) ALE rising edge after RD and WR 15 + tF 2TCL - 10 + tF t27 (CC) Address/unlatched CS hold after RD and WR 10 + tF 2TCL - 15 + tF t38 (CC) ALE falling edge to latched CS -4 - tA 10 - tA -4 - tA 10 - tA t39 (SR) Latched CS low to valid data in - 16.5 + tC+ 2tA - 3TCL - 21+ tC+ 2tA t40 (CC) Latched CS hold after RD and WR 27 + tF - 3TCL - 10.5 + tF - t42 (CC) ALE falling edge to RdCS and WrCS (with R/W delay) 7 + tA TCL - 5.5 + tA t43 (CC) ALE falling edge to RdCS and WrCS (no R/W delay) -5.5 + tA -5.5 + tA t44 (CC) Address float after RdCS and WrCS (with R/W delay)(1) - 1.5 - 1.5 t45 (CC) Address float after RdCS and WrCS (no R/W delay) 14 TCL + 1.5 t46 (SR) RdCS to valid data in (with R/W delay) 4 + tC 2TCL - 21 + tC t47 (SR) RdCS to valid data in (no R/W delay) 16.5 + tC 3TCL - 21 + tC t48 (CC) RdCS and WrCS low time (with R/W delay) 15.5 + tC - 2TCL - 9.5 + tC - t49 (CC) RdCS and WrCS low time (no R/W delay) 28 + tC 3TCL - 9.5 + tC t50 (CC) Data valid to WrCS 10 + tC 2TCL - 15 + tC t51 (SR) Data hold after RdCS 00 t52 (SR) Data float after RdCS(1) - 16.5 + tF - 2TCL - 8.5 + tF t54 (CC) Address hold after RdCS and WrCS 6 + tF - 2TCL - 19 + tF - t56 (CC) Data hold after WrCS 1. Partially tested, guaranteed by design characterization. Table 175. Multiplexed bus timings (continued) Symbol Parameter FCPU = 40 MHz TCL = 12.5 ns Variable CPU clock 1/2 TCL = 1 to 64 MHz Unit Min Max Min Max Obsolete Product(s) - Obsolete Product(s) |
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