ST10F296 datasheet(316/346 Pages) STMICROELECTRONICS

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ST10F296E

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24.8.8

Voltage controlled oscillator

The ST10F296E implements a PLL which combines different levels of frequency dividers

with a voltage controlled oscillator (VCO) working as a frequency multiplier. Table 169

presents a summary of the internal PLL settings and VCO frequencies.

The PLL input frequency range is limited to 1 to 3.5 MHz, while the VCO oscillation range is

64 to 128 MHz. The CPU clock frequency range when PLL is used is 16 to 64 MHz.

Example 1

–FXTAL = 4 MHz

–

P0(15:13) = 110 (multiplication by 3)

–

PLL input frequency = 1 MHz

–

VCO frequency = 48 MHz => Not valid

–

PLL output frequency = Not Valid

–FCPU = Not Valid

Example 2

–FXTAL = 8 MHz

–

P0(15:13) = 100 (multiplication by 5)

–

PLL input frequency = 2 MHz

–

VCO frequency = 80 MHz

–

PLL output frequency = 40 MHz (VCO frequency divided by 2)

–FCPU = 40 MHz (no effect of output prescaler)

Table 169.

Internal PLL divider mechanism

P0.15-13

(P0H.7-5)

XTAL frequency

Input

prescaler

PLL

Output

prescaler

CPU frequency

fCPU = fXTAL x F

Multiply by Divide by

114 to 8 MHz

FXTAL/4

FXTAL x 4

5.3 to 10.6 MHz

FXTAL/4

FXTAL x 3

014 to 8 MHz

FXTAL/4

FXTAL x 8

6.4 to 12 MHz

FXTAL/4

FXTAL x 5

1 to 64 MHz

–

PLL bypassed

FXTAL x 1

4 to 6.4 MHz

FXTAL/2

FXTAL x 10

4 to 12 MHz

–

PLL bypassed

FPLL/2

FXTAL/2

004 MHz

FXTAL/2

–

FXTAL x 16

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