ST72344S2 datasheet(111/247 Pages) STMICROELECTRONICS

111 / 247 page

ST72344xx, ST2345xx

On-chip peripherals

Doc ID 12321 Rev 6

111/247

Bit 5 = TOF Timer Overflow Flag.

0: No timer overflow (reset value).

1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first read

the SR register, then read or write the low byte of the CR (CLR) register.

Note:

Reading or writing the ACLR register does not clear TOF.

Bit 4 = ICF2 Input Capture Flag 2.

0: No input capture (reset value).

1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR

Bit 3 = OCF2 Output Compare Flag 2.

0: No match (reset value).

1: The content of the free running counter has matched the content of the OC2R

OC2R (OC2LR) register.

Bit 2 = TIMD Timer disable.

This bit is set and cleared by software. When set, it freezes the timer prescaler and

counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce power

consumption. Access to the timer registers is still available, allowing the timer

configuration to be changed while it is disabled.

0: Timer enabled

1: Timer prescaler, counter and outputs disabled

Bits 1:0 = Reserved, must be kept cleared.

Input capture 1 high register (IC1HR)

Reset value: Undefined

This is an 8-bit read-only register that contains the high part of the counter value (transferred

by the input capture 1 event).

Input capture 1 low register (IC1LR)

Reset value: Undefined

This is an 8-bit read only register that contains the low part of the counter value (transferred

by the input capture 1 event).

MSB

LSB

Read Only

MSB

LSB

Read Only

ST72344S2 Datasheet(PDF) 111 Page - STMicroelectronics