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ST72344S2 Datasheet(PDF) 147 Page - STMicroelectronics |
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ST72344S2 Datasheet(HTML) 147 Page - STMicroelectronics |
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147 / 247 page  ST72344xx, ST2345xx On-chip peripherals Doc ID 12321 Rev 6 147/247 Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor These 3 bits, in conjunction with the SCP1 and SCP0 bits, define the total division applied to the bus clock to yield the transmit rate clock in conventional baud rate Generator mode. Note: This TR factor is used only when the ETPR fine tuning factor is equal to 00h; otherwise, TR is replaced by the (TR*ETPR) dividing factor. Bits 2:0 = SCR[2:0] SCI Receiver rate divisor. These 3 bits, in conjunction with the SCP1 and SCP0 bits, define the total division applied to the bus clock to yield the receive rate clock in conventional Baud Rate Generator mode. Table 59. SCP[1:0] configuration PR prescaling factor SCP1 SCP0 1 0 0 31 4 1 0 13 1 Table 60. SCT[2:0] configuration TR dividing factor SCT2 SCT1 SCT0 1 0 0 0 21 4 1 0 81 16 1 0 0 32 1 64 1 0 128 1 Table 61. SCR[2:0] configuration RR dividing factor SCR2 SCR1 SCR0 1 0 0 0 21 4 1 0 81 16 1 0 0 32 1 64 1 0 128 1 |
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