ST72344S2 datasheet(151/247 Pages) STMICROELECTRONICS

151 / 247 page

ST72344xx, ST2345xx

On-chip peripherals

Doc ID 12321 Rev 6

151/247

Mode selection

The interface can operate in the four following modes:

●

Slave transmitter/receiver

●

Master transmitter/receiver

By default, it operates in slave mode.

The interface automatically switches from slave to master after it generates a START

condition, and from master to slave in case of an arbitration loss or a STOP generation,

allowing then Multi-Master capability.

Communication flow

In Master mode, it initiates a data transfer and generates the clock signal. A serial data

transfer always begins with a start condition and ends with a stop condition. Both start and

stop conditions are generated in master mode by software.

In Slave mode, the interface is capable of recognizing its own address (7 or 10-bit), and the

General Call address. The General Call address detection may be enabled or disabled by

software.

Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the

start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is

always transmitted in Master mode.

A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must

send an acknowledge bit to the transmitter. Refer to Figure 67.

Figure 67.

I2C bus protocol

Acknowledge may be enabled and disabled by software.

The I2C interface address and/or general call address can be selected by software.

The speed of the I2C interface may be selected between Standard (up to 100 kHz) and Fast

I2C (up to 400 kHz).

SDA/SCL line control

●

Transmitter mode: the interface holds the clock line low before transmission to wait for

the microcontroller to write the byte in the Data Register.

●

Receiver mode: the interface holds the clock line low after reception to wait for the

microcontroller to read the byte in the Data Register.

The SCL frequency (fSCL) is controlled by a programmable clock divider which depends on

the I2C bus mode.

SCL

SDA

MSB

ACK

Stop

Start

Condition

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