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ST72344S2 Datasheet(PDF) 164 Page - STMicroelectronics |
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ST72344S2 Datasheet(HTML) 164 Page - STMicroelectronics |
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164 / 247 page ![]() On-chip peripherals ST72344xx, ST2345xx 164/247 Doc ID 12321 Rev 6 I2C clock control register (CCR) Reset value: 0000 0000 (00h) Bit 7 = FM/SM Fast/Standard I2C mode. This bit is set and cleared by software. It is not cleared when the interface is disabled (PE=0). 0: Standard I2C mode 1: Fast I2C mode Bit 6:0 = CC[6:0] 7-bit clock divider. These bits select the speed of the bus (FSCL) depending on the I 2C mode. They are not cleared when the interface is disabled (PE=0). Refer to Section 13: Electrical characteristics for the table of values. Note: The programmed fSCL assumes no load on SCL and SDA lines. 7 0 FM/SM CC6 CC5 CC4 CC3 CC2 CC1 CC0 Read / Write |
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