ST72344S2 datasheet(165/247 Pages) STMICROELECTRONICS

165 / 247 page

ST72344xx, ST2345xx

On-chip peripherals

Doc ID 12321 Rev 6

165/247

I2C data register (DR)

Reset value: 0000 0000 (00h)

Bits 7:0 = D[7:0] 8-bit Data Register.

These bits contain the byte to be received or transmitted on the bus.

●

Transmitter mode: byte transmission start automatically when the software writes in the

DR register.

●

Receiver mode: the first data byte is received automatically in the DR register using the

least significant bit of the address.

Then, the following data bytes are received one by one after reading the DR register.

I2C own address register (OAR1)

Reset value: 0000 0000 (00h)

7-bit addressing mode

Bits 7:1 = ADD[7:1] Interface address.

These bits define the I2C bus address of the interface. They are not cleared when the

interface is disabled (PE=0).

Bit 0 = ADD0 Address direction bit.

This bit is don’t care, the interface acknowledges either 0 or 1. It is not cleared when

the interface is disabled (PE=0).

Note:

Address 01h is always ignored.

10-bit addressing mode

Bit 7:0 = ADD[7:0] Interface address.

These are the least significant bits of the I2C bus address of the interface. They are not

cleared when the interface is disabled (PE=0).

Read / Write

ADD7

ADD6

ADD5

ADD4

ADD3

ADD2

ADD1

ADD0

Read / Write

ST72344S2 Datasheet(PDF) 165 Page - STMicroelectronics