ST72344S2 datasheet(242/247 Pages) STMICROELECTRONICS

242 / 247 page

Known limitations

ST72344xx, ST2345xx

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Doc ID 12321 Rev 6

If these conditions are not met, the symptom can be avoided by implementing the following

sequence:

PUSH CC

SIM

reset interrupt flag

POP CC

16.3

16-bit timer PWM mode

In PWM mode, the first PWM pulse is missed after writing the value FFFCh in the OC1R

the OLVL1 and OLVL2 settings.

16.4

TIMD set simultaneously with OC interrupt

If the 16-bit timer is disabled at the same time the output compare event occurs then output

compare flag gets locked and cannot be cleared before the timer is enabled again.

16.4.1

Impact on the application

If output compare interrupt is enabled, then the output compare flag cannot be cleared in the

timer interrupt routine. Consequently, the interrupt service routine is called repeatedly.

16.4.2

Workaround

Disable the timer interrupt before disabling the timer. Again while enabling, first enable the

timer then the timer interrupts.

Perform the following to disable the timer:

TACR1 = 0x00h; // Disable the compare interrupt

TACSR |= 0x40; // Disable the timer

Perform the following to enable the timer again:

TACSR &= ~0x40; // Enable the timer

TACR1 = 0x40; // Enable the compare interrupt

16.5

SCI wrong break duration

16.5.1

Description

A single break character is sent by setting and resetting the SBK bit in the SCICR2 register.

In some cases, the break character may have a longer duration than expected:

●

20 bits instead of 10 bits if M=0

●

22 bits instead of 11 bits if M=1

In the same way, as long as the SBK bit is set, break characters are sent to the TDO pin.

This may lead to generate one break more than expected.

ST72344S2 Datasheet(PDF) 242 Page - STMicroelectronics

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