ST72344S2 datasheet(243/247 Pages) STMICROELECTRONICS

243 / 247 page

ST72344xx, ST2345xx

Known limitations

Doc ID 12321 Rev 6

243/247

16.5.2

Occurrence

The occurrence of the problem is random and proportional to the baud rate. With a transmit

frequency of 19200 baud (fCPU=8 MHz and SCIBRR=0xC9), the wrong break duration

occurrence is around 1%.

16.5.3

Workaround

If this wrong duration is not compliant with the communication protocol in the application,

software can request that an Idle line be generated before the break character. In this case,

the break duration is always correct assuming the application is not doing anything between

the idle and the break. This can be ensured by temporarily disabling interrupts.

The exact sequence is:

●

Disable interrupts

●

Reset and Set TE (IDLE request)

●

Set and Reset SBK (Break request)

●

Re-enable interrupts

16.6

Random read operations not supported with the standard I²C

16.6.1

Description

The standard I²C peripheral is not fully compliant with random read capabilities (only the

I2C3SNS interface supports these capabilities). If the master sends a Restart condition, a

bus error is generated on the ST7 device in slave mode.

16.6.2

Occurrence

The occurrence of the problem is random.

16.6.3

Workaround

The Restart condition is not allowed. The master must not send a Restart condition. It must

send a Stop condition before a second Start (each Start has to be preceded by a Stop).

16.7

Programming of EEPROM data

16.7.1

Description

In user mode, when programming EEPROM data memory, the read access to the program

memory between E000h and FFFFh can be corrupted.

16.7.2

Impact on application

The EEPROM programming routine must be located outside this program memory area.

Any access to the interrupt vector table can result in an unexpected code being executed, so

the interrupts must be masked.

ST72344S2 Datasheet(PDF) 243 Page - STMicroelectronics

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