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ST72325AR7-Auto Datasheet(PDF) 71 Page - STMicroelectronics |
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ST72325AR7-Auto Datasheet(HTML) 71 Page - STMicroelectronics |
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71 / 243 page  Obsolete Product(s) - Obsolete Product(s) ST72325xxx-Auto Power saving modes Doc ID 13770 Rev 3 71/243 ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). The compatibility of Watchdog operation with Halt mode is configured by the ‘WDGHALT’ option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see Section 21.1.1: Flash configuration for more details). Figure 29. Halt timing overview HALT RUN RUN 256 OR 4096 CPU CYCLE DELAY RESET OR INTERRUPT HALT INSTRUCTION FETCH VECTOR [MCCSR.OIE = 0] |
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