ST72325AR7-Auto datasheet(72/243 Pages) STMICROELECTRONICS

72 / 243 page

Obsolete

Product(s)

- Obsolete

Product(s)

Power saving modes

ST72325xxx-Auto

72/243

Doc ID 13770 Rev 3

Figure 30.

Halt mode flowchart

WDGHALT is an option bit. See Section 21.1.1: Flash configurationfor more details.

Peripheral clocked with an external clock source can still be active.

Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to

Table 21: Interrupt mappingfor more details.

Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are

set to the current software priority level of the interrupt routine and recovered when the CC register is

popped.

HALT INSTRUCTION

RESET

INTERRUPT (3)

CPU

OSCILLATOR

PERIPHERALS (2)

I[1:0] BITS

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

OFF

XX (4)

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

XX (4)

256 OR 4096 CPU CLOCK

DELAY

WATCHDOG

ENABLE

DISABLE

WDGHALT (1)

WATCHDOG

RESET

(MCCSR.OIE = 0)

CYCLE

ST72325AR7-Auto Datasheet(PDF) 72 Page - STMicroelectronics

ST72325AR7-Auto Datasheet(HTML) 72 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL