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ST72325AR7-Auto Datasheet(PDF) 217 Page - STMicroelectronics |
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ST72325AR7-Auto Datasheet(HTML) 217 Page - STMicroelectronics |
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217 / 243 page  Obsolete Product(s) - Obsolete Product(s) ST72325xxx-Auto Electrical characteristics Doc ID 13770 Rev 3 217/243 19.11.2 I2C - inter IC control interface Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Refer to Section 19.8: I/O port pin characteristics for more details on the input/output alternate function characteristics (SDAI and SCLI). The ST7 I2C interface meets the requirements of the standard I2C communication protocol described in the following table. Table 135. I2C control interface characteristics Symbol Parameter Standard mode I2CFast mode I2C(1) Unit Min(2) Max(2) Min(2) Max(2) tw(SCLL) SCL clock low time 4.7 1.3 µs tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 ns th(SDA) SDA data hold time 0(3) 0(4) 900(3) tr(SDA) tr(SCL) SDA and SCL rise time 1000 20+0.1Cb 300 tf(SDA) tf(SCL) SDA and SCL fall time 300 th(STA) START condition hold time 4.0 0.6 µs tsu(STA) Repeated START condition setup time 4.7 tsu(STO) STOP condition setup time 4.0 tw(STO:STA) STOP to START condition time (bus free) 4.7 1.3 Cb Capacitive load for each bus line 400 400 pF 1. At 4 MHz fCPU, maximum I 2C speed (400 kHz) is not achievable. In this case, maximum I2C speed will be approximately 260 kHz. 2. Data based on standard I2C protocol requirement, not tested in production. 3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL signal. 4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. |
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