ST72325AR7-Auto datasheet(236/243 Pages) STMICROELECTRONICS

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Known limitations

ST72325xxx-Auto

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Doc ID 13770 Rev 3

Known limitations

22.1

All devices

22.1.1

Unexpected reset fetch

If an interrupt request occurs while a “POP CC” instruction is executed, the interrupt

controller does not recognize the source of the interrupt and, by default, passes the RESET

vector address to the CPU.

Workaround

To solve this issue, a “POP CC” instruction must always be preceded by a “SIM” instruction.

22.1.2

External interrupt missed

To avoid any risk of generating a parasitic interrupt, the edge detector is automatically

disabled for one clock cycle during an access to either DDR and OR. Any input signal edge

during this period will not be detected and will not generate an interrupt.

This case can typically occur if the application refreshes the port configuration registers at

intervals during runtime.

Workaround

The workaround is based on software checking the level on the interrupt pin before and after

writing to the PxOR or PxDDR registers. If there is a level change (depending on the

sensitivity programmed for this pin) the interrupt routine is invoked using the call instruction

with three extra PUSH instructions before executing the interrupt routine (this is to make the

call compatible with the IRET instruction at the end of the interrupt service routine).

But detection of the level change does not make sure that edge occurs during the critical 1

cycle duration and the interrupt has been missed. This may lead to occurrence of same

interrupt twice (one hardware and another with software call).

To avoid this, a semaphore is set to ‘1’ before checking the level change. The semaphore is

changed to level '0' inside the interrupt routine. When a level change is detected, the

semaphore status is checked. If it is ‘1’, it means that the last interrupt has been missed. In

this case, the interrupt routine is invoked with the call instruction.

There is another possible case, that is, if PxOR or PxDDR are written to with global

interrupts disabled (interrupt mask bit set). In this case, the semaphore is changed to ‘1’

when the level change is detected. Detecting a missed interrupt is done after the global

interrupts are enabled (interrupt mask bit reset) and by checking the status of the

semaphore. If it is ‘1’, it means that the last interrupt was missed and the interrupt routine is

invoked with the call instruction.

To implement the workaround, the following software sequence is to be followed for writing

into the PxOR/PxDDR registers. The example is for Port PF1 with falling edge interrupt

sensitivity. The software sequence is given for both cases (global interrupts disabled / global

interrupts enabled):

Case 1: Writing to PxOR or PxDDR with global interrupts enabled:

LD A,#01

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