ST72361AR4-Auto datasheet(119/279 Pages) STMICROELECTRONICS

119 / 279 page

ST72361xx-Auto

16-bit timer

Doc ID 12468 Rev 3

119/279

Bit 6 = OCF1 Output Compare Flag 1.

0: nomatch (reset value).

1: the content of the free running counter has matched the content of the OC1R

OC1R (OC1LR) register.

Bit 5 = TOF Timer Overflow Flag.

0: No timer overflow (reset value).

1:The free running counter rolled over from FFFFh to 0000h. To clear this bit, first read

the SR register, then read or write the low byte of the CR (CLR) register.

Note: Reading or writing the ACLR register does not clear TOF.

Bit 4 = ICF2 Input Capture Flag 2.

0: No input capture (reset value).

1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR

Bit 3 = OCF2 Output Compare Flag 2.

0: No match (reset value).

1: The content of the free running counter has matched the content of the OC2R

OC2R (OC2LR) register.

Bit 2 = TIMD Timer disable.

This bit is set and cleared by software. When set, it freezes the timer prescaler and counter

and disabled the output functions (OCMP1 and OCMP2 pins) to reduce power consumption.

Access to the timer registers is still available, allowing the timer configuration to be changed,

or the counter reset, while it is disabled.

0: Timer enabled

1: Timer prescaler, counter and outputs disabled

Bits 1:0 = Reserved, must be kept cleared.

12.7.4

Input capture 1 high register (IC1HR)

Read Only

Reset value: Undefined

This is an 8-bit read only register that contains the high part of the counter value (transferred

by the input capture 1 event).

MSB

LSB

ST72361AR4-Auto Datasheet(PDF) 119 Page - STMicroelectronics