ST72361AR4-Auto datasheet(116/279 Pages) STMICROELECTRONICS

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16-bit timer

ST72361xx-Auto

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Doc ID 12468 Rev 3

Note:

The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts

chapter). These events generate an interrupt if the corresponding Enable Control Bit is set

and the interrupt mask in the CC register is reset (RIM instruction).

12.6

Summary of timer modes

12.7

Each Timer is associated with three control and status registers, and with six pairs of data

registers (16-bit values) relating to the two input captures, the two output compares, the

counter and the alternate counter.

12.7.1

Control register 1 (CR1)

Read/ write

Reset value: 0000 0000 (00h)

Bit 7 = ICIE Input Capture Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set.

Bit 6 = OCIE Output Compare Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is

set.

Table 49.

Timer modes

Modes

Timer resources

Input capture 1

Input capture 2

Output compare 1 Output compare 2

Input capture

(1 and/or 2)

Yes

Output compare

(1 and/or 2)

One pulse mode

Not

recommended(1)

See note 4 in One pulse mode

Partially (2)

See note 5 in One pulse mode

PWM Mode

Not

recommended(3)

See note 4 in Pulse width modulation mode

ICIE

OCIE

TOIE

FOLV2

FOLV1

OLVL2

IEDG1

OLVL1

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