ST72361AR4-Auto datasheet(126/279 Pages) STMICROELECTRONICS

126 / 279 page

8-bit timer (TIM8)

ST72361xx-Auto

126/279

Doc ID 12468 Rev 3

Figure 59.

Timer block diagram

Whatever the timer mode used (input capture, output compare, one pulse mode or PWM

mode) an overflow occurs when the counter rolls over from FFh to 00h then:

●

The TOF bit of the SR register is set.

●

A timer interrupt is generated if:

–

TOIE bit of the CR1 register is set and

–

I bit of the CC register is cleared.

If one of these conditions is false, the interrupt remains pending to be issued as soon as

they are both true.

Clearing the overflow interrupt request is done in two steps:

MCU-PERIPHERAL INTERFACE

COUNTER

ALTERNATE

OUTPUT

COMPARE

OUTPUT COMPARE

EDGE DETECT

OVERFLOW

DETECT

CIRCUIT

1/2

1/4

1/8

ST7 INTERNAL BUS

LATCH1

OCMP1

ICAP1

fCPU

TIMER INTERRUPT

ICF2

ICF1

TIMD

OCF2

OCF1 TOF

PWM

OC1E

IEDG2

CC0

CC1

OC2E OPM

FOLV2

ICIE

OLVL1

IEDG1

OLVL2

FOLV1

OCIE TOIE

ICAP2

LATCH2

OCMP2

(Control Register 1) CR1

(Control Register 2) CR2

(Control/Status Register)

TIMER INTERNAL BUS

CIRCUIT1

EDGE DETECT

CIRCUIT2

CIRCUIT

OUTPUT

COMPARE

INPUT

CAPTURE

INPUT

CAPTURE

CC[1:0]

COUNTER

Note: If IC, OC and TO interrupt requests have separate vectors

then the last OR is not present (See device Interrupt Vector Table)

(See note)

CSR

1/8000

fOSC2

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