ST72361AR4-Auto datasheet(161/279 Pages) STMICROELECTRONICS

161 / 279 page

ST72361xx-Auto

LINSCI serial communication interface (LIN master/slave)

Doc ID 12468 Rev 3

161/279

Idle line

Setting the TE bit drives the SCI to send a preamble of 10 (M = 0) or 11 (M = 1) consecutive

‘1’s (idle line) before the first character.

In this case, clearing and then setting the TE bit during a transmission sends a preamble

(idle line) after the current word. Note that the preamble duration (10 or 11 consecutive ‘1’s

depending on the M bit) does not take into account the stop bit of the previous character.

Note:

Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the

best time to toggle the TE bit is when the TDRE bit is set, that is, before writing the next byte

in the SCIDR.

15.5.5

Receiver

The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9

bits and the MSB is stored in the R8 bit in the SCICR1 register.

Character reception

During a SCI reception, data shifts in least significant bit first through the RDI pin. In this

mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the

received shift register (see Figure 77).

Procedure

●

Select the M bit to define the word length.

●

Select the desired baud rate using the SCIBRR and the SCIERPR registers.

●

Set the RE bit, this enables the receiver which begins searching for a start bit.

When a character is received:

●

The RDRF bit is set. It indicates that the content of the shift register is transferred to the

RDR.

●

An interrupt is generated if the RIE bit is set and the I[1:0] bits are cleared in the CCR

●

The error flags can be set if a frame error, noise or an overrun error has been detected

during reception.

Clearing the RDRF bit is performed by the following software sequence done by:

1. An access to the SCISR register

2. A read to the SCIDR register.

The RDRF bit must be cleared before the end of the reception of the next character to avoid

an overrun error.

Idle line

When an idle line is detected, there is the same procedure as a data received character plus

an interrupt if the ILIE bit is set and the I[|1:0] bits are cleared in the CCR register.

Overrun error

An overrun error occurs when a character is received when RDRF has not been reset. Data

can not be transferred from the shift register to the TDR register as long as the RDRF bit is

not cleared.

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