ST72361AR4-Auto datasheet(165/279 Pages) STMICROELECTRONICS

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ST72361xx-Auto

LINSCI serial communication interface (LIN master/slave)

Doc ID 12468 Rev 3

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Idle line detection

Receiver wakes up by idle line detection when the receive line has recognized an Idle Line.

Then the RWU bit is reset by hardware but the IDLE bit is not set.

This feature is useful in a multiprocessor system when the first characters of the message

determine the address and when each message ends by an idle line: As soon as the line

becomes idle, every receivers is waken up and analyze the first characters of the message

which indicates the addressed receiver. The receivers which are not addressed set RWU bit

to enter in mute mode. Consequently, they will not treat the next characters constituting the

next part of the message. At the end of the message, an idle line is sent by the transmitter:

this wakes up every receivers which are ready to analyze the addressing characters of the

new message.

In such a system, the inter-characters space must be smaller than the idle time.

Address mark detection

Receiver wakes up by address mark detection when it received a “1” as the most significant

bit of a word, thus indicating that the message is an address. The reception of this particular

word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the

receiver to receive this word normally and to use it as an address word.

This feature is useful in a multiprocessor system when the most significant bit of each

character (except for the break character) is reserved for Address Detection. As soon as the

receivers received an address character (most significant bit = ’1’), the receivers are waken

up. The receivers which are not addressed set RWU bit to enter in mute mode.

Consequently, they will not treat the next characters constituting the next part of the

message.

15.5.8

Parity control

Hardware byte Parity control (generation of parity bit in transmission and parity checking in

reception) can be enabled by setting the PCE bit in the SCICR1 register. Depending on the

character format defined by the M bit, the possible SCI character formats are as listed in

Table 60.

Note:

In case of wake-up by an address mark, the MSB bit of the data is taken into account and

not the parity bit

Even parity

The parity bit is calculated to obtain an even number of “1s” inside the character made of the

7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.

Table 60.

Character formats(1)

SB = Start Bit, STB = Stop Bit, PB = Parity Bit

M bit

PCE bit

Character format

|SB| 8 bit data |STB|

|SB| 7-bit data |PB|STB|

|SB| 9-bit data |STB|

|SB| 8-bit data |PB|STB|

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