ST72361AR4-Auto datasheet(168/279 Pages) STMICROELECTRONICS

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LINSCI serial communication interface (LIN master/slave)

ST72361xx-Auto

168/279

Doc ID 12468 Rev 3

The OR bit is set by hardware when the word currently being received in the shift register is

ready to be transferred into the RDR register whereas RDRF is still set. An interrupt is

generated if RIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access

to the SCISR register followed by a read to the SCIDR register).

0: no overrun error

1: overrun error detected

Note:

When this bit is set, RDR register contents will not be lost but the shift register will be

overwritten.

Bit 2 = NF Character Noise flag

This bit is set by hardware when noise is detected on a received character. It is cleared by a

software sequence (an access to the SCISR register followed by a read to the SCIDR

0: no noise

1: noise is detected

Note:

This bit does not generate interrupt as it appears at the same time as the RDRF bit which

itself generates an interrupt.

Bit 1 = FE Framing error.

This bit is set by hardware when a desynchronization, excessive noise or a break character

is detected. It is cleared by a software sequence (an access to the SCISR register followed

by a read to the SCIDR register).

0: no Framing error

1: framing error or break character detected

Note:

This bit does not generate an interrupt as it appears at the same time as the RDRF bit which

itself generates an interrupt. If the word currently being transferred causes both a frame

error and an overrun error, it will be transferred and only the OR bit will be set.

Bit 0 = PE Parity error.

This bit is set by hardware when a byte parity error occurs (if the PCE bit is set) in receiver

mode. It is cleared by a software sequence (a read to the status register followed by an

access to the SCIDR data register). An interrupt is generated if PIE = 1 in the SCICR1

0: no parity error

1: parity error detected

15.8.2

Control register 1 (SCICR1)

Read/ write

Reset value: x000 0000 (x0h)

Bit 7 = R8 Receive data bit 8.

This bit is used to store the 9th bit of the received word when M = 1.

Bit 6 = T8 Transmit data bit 8.

This bit is used to store the 9th bit of the transmitted word when M = 1.

SCID

WAKE

PCE(1)

This bit has a different function in LIN mode, please refer to the LIN mode register description.

PIE

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