ST72361AR4-Auto datasheet(171/279 Pages) STMICROELECTRONICS

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ST72361xx-Auto

LINSCI serial communication interface (LIN master/slave)

Doc ID 12468 Rev 3

171/279

Contains the received or transmitted data character, depending on whether it is read from or

written to.

The data register performs a double function (read and write) since it is composed of two

registers, one for transmission (TDR) and one for reception (RDR).

The TDR register provides the parallel interface between the internal bus and the output

shift register (see Figure 77).

The RDR register provides the parallel interface between the input shift register and the

internal bus (see Figure 77).

15.8.5

Baud rate register (SCIBRR)

Read/ write

Reset value: 0000 0000 (00h)

Note:

When LIN slave mode is disabled, the SCIBRR register controls the conventional baud rate

generator.

Bits 7:6 = SCP[1:0] First SCI Prescaler

These 2 prescaling bits allow several standard clock division ranges

Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor

These 3 bits, in conjunction with the SCP1 and SCP0 bits define the total division applied to

the bus clock to yield the transmit rate clock in conventional Baud Rate Generator mode.

DR7

DR6

DR5

DR4

DR3

DR2

DR1

DR0

SCP1

SCP0

SCT2

SCT1

SCT0

SCR2

SCR1

SCR0

Table 63.

PR prescaler

PR prescaling factor

SCP1

SCP0

Table 64.

Transmitter rate divider

TR dividing factor

SCT2

SCT1

SCT0

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