ST72361AR4-Auto datasheet(169/279 Pages) STMICROELECTRONICS

169 / 279 page

ST72361xx-Auto

LINSCI serial communication interface (LIN master/slave)

Doc ID 12468 Rev 3

169/279

Bit 5 = SCID Disabled for low power consumption

When this bit is set the SCI prescalers and outputs are stopped and the end of the current

byte transfer in order to reduce power consumption.This bit is set and cleared by software.

0: SCI enabled

1: SCI prescaler and outputs disabled

Bit 4 = M Word length.

This bit determines the word length. It is set or cleared by software.

0: 1 start bit, 8 data bits, 1 stop bit

1: 1 start bit, 9 data bits, 1 stop bit

Note:

The M bit must not be modified during a data transfer (both transmission and reception).

Bit 3 = WAKE Wake-Up method.

This bit determines the SCI Wake-Up method, it is set or cleared by software.

0: idle line

1: address mark

Note:

If the LINE bit is set, the WAKE bit is deactivated and replaced by the LHDM bit.

Bit 2 = PCE Parity control enable.

This bit is set and cleared by software. It selects the hardware parity control (generation and

detection for byte parity, detection only for LIN parity).

0: parity control disabled

1: parity control enabled

Bit 1 = PS Parity selection.

This bit selects the odd or even parity when the parity generation/detection is enabled (PCE

bit set). It is set and cleared by software. The parity will be selected after the current byte.

0: even parity

1: odd parity

Bit 0 = PIE Parity interrupt enable.

This bit enables the interrupt capability of the hardware parity control when a parity error is

detected (PE bit set). The parity error involved can be a byte parity error (if bit PCE is set

and bit LPE is reset) or a LIN parity error (if bit PCE is set and bit LPE is set).

0: parity error interrupt disabled

1: parity error interrupt enabled

15.8.3

Control register 2 (SCICR2)

Read/ write

Reset value: 0000 0000 (00h)

Bit 7 = TIE Transmitter interrupt enable.

This bit is set and cleared by software.

0: interrupt is inhibited

1: in SCI interrupt is generated whenever TDRE = 1 in the SCISR register

TIE

TCIE

RIE

ILIE

RWU(1)

This bit has a different function in LIN mode, please refer to the LIN mode register description.

SBK(1)

ST72361AR4-Auto Datasheet(PDF) 169 Page - STMicroelectronics

ST72361AR4-Auto Datasheet(HTML) 169 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL