ST72361AR4-Auto datasheet(177/279 Pages) STMICROELECTRONICS

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ST72361xx-Auto

LINSCI serial communication interface (LIN master/slave)

Doc ID 12468 Rev 3

177/279

15.9.4

LIN error detection

LIN header error flag

The LIN header error flag indicates that an invalid LIN header has been detected.

When a LIN header error occurs:

●

The LHE flag is set

●

An interrupt is generated if the RIE bit is set and the I[1:0] bits are cleared in the CCR

If autosynchronization is enabled (LASE bit = 1), this can mean that the LIN synch field is

corrupted, and that the SCI is in a blocked state (LSF bit is set). The only way to recover is to

reset the LSF bit and then to clear the LHE bit.

●

The LHE bit is reset by an access to the SCISR register followed by a read of the

SCIDR register.

LHE/OVR error conditions

When auto resynchronization is disabled (LASE bit = 0), the LHE flag detects:

●

That the received LIN synch field is not equal to 55h.

●

That an overrun occurred (as in standard SCI mode)

●

Furthermore, if LHDM is set it also detects that a LIN header reception timeout

occurred (only if LHDM is set).

When the LIN auto-resynchronization is enabled (LASE bit = 1), the LHE flag detects:

●

That the deviation error on the synch field is outside the LIN specification which allows

up to +/-15.5% of period deviation between the slave and master oscillators.

●

A LIN header reception timeout occurred.

If THEADER > THEADER_MAX then the LHE flag is set. Refer to Figure 82. (only if LHDM

is set to 1)

●

An overflow during the synch field measurement, which leads to an overflow of the

divider registers. If LHE is set due to this error then the SCI goes into a blocked state

(LSF bit is set).

●

That an overrun occurred on fields other than the synch field (as in standard SCI mode)

Deviation error on the synch field

The deviation error is checking by comparing the current baud rate (relative to the slave

oscillator) with the received LIN synch field (relative to the master oscillator). Two checks are

performed in parallel:

●

The first check is based on a measurement between the first falling edge and the last

falling edge of the synch field. Let us refer to this period deviation as D:

Identifier Field

parity bits

ID0

start bit

stop bit

ID1 ID2 ID3 ID4 ID5 P0 P1

identifier bits

ID1

ID3

ID4

ID5





ID0

ID1

ID2

ID4





M= 0

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