ST72361AR4-Auto datasheet(181/279 Pages) STMICROELECTRONICS

181 / 279 page

ST72361xx-Auto

LINSCI serial communication interface (LIN master/slave)

Doc ID 12468 Rev 3

181/279

Figure 84.

LDIV read / write operations when LDUM = 0

Figure 85.

LDIV read / write operations when LDUM = 1

15.9.7

LINSCI clock tolerance

LINSCI clock tolerance when unsynchronized

When LIN slaves are unsynchronized (meaning no characters have been transmitted for a

relatively long time), the maximum tolerated deviation of the LINSCI clock is +/-15%.

If the deviation is within this range then the LIN synch break is detected properly when a

new reception occurs.

This is made possible by the fact that masters send 13 low bits for the LIN synch break,

which can be interpreted as 11 low bits (13 bits -15% = 11.05) by a “fast” slave and then

considered as a LIN synch break. According to the LIN specification, a LIN synch break is

valid when its duration is greater than tSBRKTS = 10. This means that the LIN synch break

must last at least 11 low bits.

MANT(7:0)

LDIV

FRAC(3:0)

LDIV_NOM

Baud Rate

Read LPR

Write LPFR

Update

at end of

Synch Field

FRAC(3:0)

MANT(7:0)

LDIV_MEAS

FRAC(3:0)

MANT(7:0)

Write LPR

Read LPFR

Generation

LIN Sync Field

Measurement

Write LPR

MANT(7:0)

LDIV

FRAC(3:0)

LDIV_NOM

Baud Rate

Read LPR

Write LPFR

Update

RDRF = 1

at end of

Synch Field

FRAC(3:0)

MANT(7:0)

LDIV_MEAS

FRAC(3:0)

MANT(7:0)

Write LPR

Read LPFR

Generation

LIN Sync Field

Measurement

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