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ST72361AR4-Auto Datasheet(PDF) 185 Page - STMicroelectronics

Part # ST72361AR4-Auto
Description  Clock, reset and supply management
PDF  279 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72361AR4-Auto Datasheet(HTML) 185 Page - STMicroelectronics

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ST72361xx-Auto
LINSCI serial communication interface (LIN master/slave)
Doc ID 12468 Rev 3
185/279
15.10.2
Control Register 1 (SCICR1)
Read/ write
Reset value: x000 0000 (x0h)
Bits 7:3 = Same function as in SCI mode, please refer to Section 15.8: SCI mode register
description.
Bit 2 = PCE Parity control enable.
This bit is set and cleared by software. It selects the hardware parity control for LIN identifier
parity check.
0: parity control disabled
1: parity control enabled
When a parity error occurs, the PE bit in the SCISR register is set.
Bit 1 = reserved
Bit 0 = same function as in SCI mode, please refer to Section 15.8: SCI mode register
description.
15.10.3
Control Register 2 (SCICR2)
Read/ write
Reset value: 0000 0000 (00h)
Bits 7:2 = same function as in SCI mode, please refer to Section 15.8: SCI mode register
description.
Bit 1 = RWU Receiver wake-up.
This bit determines if the SCI is in mute mode or not. It is set and cleared by software and
can be cleared by hardware when a wake-up sequence is recognized.
0: receiver in active mode
1: receiver in mute mode
Note:
Mute mode is recommended for detecting only the header and avoiding the reception of any
other characters. For more details please refer to LIN reception.
In LIN slave mode, when RDRF is set, the software can not set or clear the RWU bit.
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is set and cleared by software.
0: no break character is transmitted
1: break characters are transmitted
Note:
If the SBK bit is set to “1” and then to “0”, the transmitter will send a BREAK word at the end
of the current word.
7
0
R8
T8
SCID
M
WAKE
PCE
PS
PIE
7
0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK



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