ST72361AR4-Auto datasheet(183/279 Pages) STMICROELECTRONICS

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ST72361xx-Auto

LINSCI serial communication interface (LIN master/slave)

Doc ID 12468 Rev 3

183/279

15.9.9

Error due to LIN synch measurement

The LIN synch field is measured over eight bit times.

This measurement is performed using a counter clocked by the CPU clock. The edge

detections are performed using the CPU clock cycle.

This leads to a precision of 2 CPU clock cycles for the measurement which lasts 16*8*LDIV

clock cycles.

Consequently, this error (DMEAS) is equal to:

2 / (128*LDIVMIN).

LDIVMIN corresponds to the minimum LIN prescaler content, leading to the maximum baud

rate, taking into account the maximum deviation of +/-15%.

15.9.10

Error due to baud rate quantization

The baud rate can be adjusted in steps of 1 / (16 * LDIV). The worst case occurs when the

“real” baud rate is in the middle of the step.

This leads to a quantization error (DQUANT) equal to 1 / (2*16*LDIVMIN).

15.9.11

Impact of clock deviation on maximum baud rate

The choice of the nominal baud rate (LDIVNOM) will influence both the quantization error

(DQUANT) and the measurement error (DMEAS). The worst case occurs for LDIVMIN.

Consequently, at a given CPU frequency, the maximum possible nominal baud rate

(LPRMIN) should be chosen with respect to the maximum tolerated deviation given by the

equation:

DTRA + 2 / (128 * LDIVMIN) + 1 / (2 *16 * LDIVMIN) + DREC + DTCL < 3.75%

Example:

A nominal baud rate of 20Kbits/s at TCPU = 125ns (8 MHz) leads to LDIVNOM = 25d.

LDIVMIN = 25 - 0.15*25 = 21.25

DMEAS = 2 / (128 * LDIVMIN) * 100 = 0.00073%

DQUANT = 1 / (2 * 16 * LDIVMIN) * 100 = 0.0015%

LIN slave systems

For LIN slave systems (the LINE and LSLV bits are set), receivers wake up by LIN synch

break or LIN Identifier detection (depending on the LHDM bit).

Hot plugging feature for LIN slave nodes

In LIN slave mute mode (the LINE, LSLV and RWU bits are set) it is possible to hot plug to a

network during an ongoing communication flow. In this case the SCI monitors the bus on the

RDI line until 11 consecutive dominant bits have been detected and discards all the other

bits received.

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