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ST72361AR4-Auto Datasheet(PDF) 196 Page - STMicroelectronics |
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ST72361AR4-Auto Datasheet(HTML) 196 Page - STMicroelectronics |
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196 / 279 page  LINSCI serial communication interface (LIN master only) ST72361xx-Auto 196/279 Doc ID 12468 Rev 3 Refer to the register descriptions in Section 15.8: SCI mode register descriptionfor the definitions of each bit. 16.4.1 Serial data format Word length may be selected as being either 8 or 9 bits by programming the M bit in the SCICR1 register (see Figure 89). The TDO pin is in low state during the start bit. The TDO pin is in high state during the stop bit. An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next frame which contains data. A break character is interpreted on receiving “0”s for some multiple of the frame period. At the end of the last break frame the transmitter inserts an extra “1” bit to acknowledge the start bit. Transmission and reception are driven by their own baud rate generator. Figure 89. Word length programming 16.4.2 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the T8 bit in the SCICR1 register. When the transmit enable bit (TE) is set, the data in the transmit shift register is output on the TDO pin and the corresponding clock pulses are output on the SCLK pin. Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Start Bit Stop Bit Next Start Bit Idle Frame Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Start Bit Stop Bit Next Start Bit Idle Frame Start Bit 9-bit Word length (M bit is set) 8-bit Word length (M bit is reset) Possible Parity Bit Possible Parity Bit Break Frame Start Bit Extra ’1’ Data Frame Break Frame Start Bit Extra ’1’ Data Frame Next Data Frame Next Data Frame Start Bit **** ** LBCL bit controls last data clock pulse CLOCK CLOCK ** LBCL bit controls last data clock pulse ** ** |
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