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ST72361AR4-Auto Datasheet(PDF) 198 Page - STMicroelectronics |
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ST72361AR4-Auto Datasheet(HTML) 198 Page - STMicroelectronics |
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198 / 279 page ![]() LINSCI serial communication interface (LIN master only) ST72361xx-Auto 198/279 Doc ID 12468 Rev 3 Idle characters Setting the TE bit drives the SCI to send an idle frame before the first data frame. Clearing and then setting the TE bit during a transmission sends an idle frame after the current word. Note: Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the best time to toggle the TE bit is when the TDRE bit is set, that is, before writing the next byte in the SCIDR. LIN transmission The same procedure has to be applied for LIN master transmission with the following differences: ● Clear the M bit to configure 8-bit word length. ● Set the LINE bit to enter LIN master mode. In this case, setting the SBK bit sends 13 low bits. 16.4.3 Receiver The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the SCICR1 register. Character reception During a SCI reception, data shifts in least significant bit first through the RDI pin. In this mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the received shift register (see Figure 88). Procedure ● Select the M bit to define the word length. ● Select the desired baud rate using the SCIBRR and the SCIERPR registers. ● Set the RE bit, this enables the receiver which begins searching for a start bit. When a character is received: ● The RDRF bit is set. It indicates that the content of the shift register is transferred to the RDR. ● An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register. ● The error flags can be set if a frame error, noise or an overrun error has been detected during reception. Clearing the RDRF bit is performed by the following software sequence done by: 1. An access to the SCISR register 2. A read to the SCIDR register. The RDRF bit must be cleared before the end of the reception of the next character to avoid an overrun error. Break character When a break character is received, the SCI handles it as a framing error. |
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