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ST72361AR4-Auto Datasheet(PDF) 202 Page - STMicroelectronics

Part # ST72361AR4-Auto
Description  Clock, reset and supply management
PDF  279 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72361AR4-Auto Datasheet(HTML) 202 Page - STMicroelectronics

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LINSCI serial communication interface (LIN master only)
ST72361xx-Auto
202/279
Doc ID 12468 Rev 3
Receiver wakes-up by address mark detection when it received a “1” as the most significant
bit of a word, thus indicating that the message is an address. The reception of this particular
word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the
receiver to receive this word normally and to use it as an address word.
16.4.7
Parity control
Parity control (generation of parity bit in transmission and parity checking in reception) can
be enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length
defined by the M bit, the possible SCI frame formats are as listed in Table 72.
Note:
In case of wake up by an address mark, the MSB bit of the data is taken into account and
not the parity bit.
Even parity
The parity bit is calculated to obtain an even number of “1s” inside the frame made of the 7
or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Example 1:
data = 00110101; 4 bits set => parity bit is 0 if even parity is selected (PS bit = 0).
Odd parity
The parity bit is calculated to obtain an odd number of “1s” inside the frame made of the 7 or
8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit is 1 if odd parity is selected (PS bit = 1).
Transmission mode
If the PCE bit is set then the MSB bit of the data written in the data register is not transmitted
but is changed by the parity bit.
Reception mode
If the PCE bit is set then the interface checks if the received data byte has an even number
of “1s” if even parity is selected (PS = 0) or an odd number of “1s” if odd parity is selected
(PS = 1). If the parity check fails, the PE flag is set in the SCISR register and an interrupt is
generated if PIE is set in the SCICR1 register.
Table 72.
Frame formats
M bit
PCE bit
SCI frame(1)
1.
SB: start bit
STB: stop bit
PB: parity bit
0
0
| SB | 8 bit data | STB |
1
| SB | 7-bit data | PB | STB |
1
0
| SB | 9-bit data | STB |
1
| SB | 8-bit data PB | STB |



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