ST72361AR4-Auto datasheet(206/279 Pages) STMICROELECTRONICS

206 / 279 page

LINSCI serial communication interface (LIN master only)

ST72361xx-Auto

206/279

Doc ID 12468 Rev 3

software sequence (an access to the SCISR register followed by a read to the SCIDR

0: data is not received

1: received data is ready to be read

Bit 4 = IDLE Idle line detect.

This bit is set by hardware when an Idle Line is detected. An interrupt is generated if the

ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the

SCISR register followed by a read to the SCIDR register).

0: no idle line is detected

1: idle line is detected

Note:

The IDLE bit is not be set again until the RDRF bit has been set itself (that is, a new idle line

occurs).

Bit 3 = OR Overrun error.

This bit is set by hardware when the word currently being received in the shift register is

ready to be transferred into the RDR register while RDRF = 1. An interrupt is generated if

RIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the

SCISR register followed by a read to the SCIDR register).

0: no overrun error

1: overrun error is detected

Note:

When this bit is set, the RDR register content is not lost but the shift register is overwritten.

Bit 2 = NF Noise flag.

This bit is set by hardware when noise is detected on a received frame. It is cleared by a

software sequence (an access to the SCISR register followed by a read to the SCIDR

0: no noise is detected

1: noise is detected

Note:

This bit does not generate interrupt as it appears at the same time as the RDRF bit which

itself generates an interrupt.

Bit 1 = FE Framing error.

This bit is set by hardware when a de-synchronization, excessive noise or a break character

is detected. It is cleared by a software sequence (an access to the SCISR register followed

by a read to the SCIDR register).

0: no framing error is detected

1: framing error or break character is detected

Note:

This bit does not generate an interrupt as it appears at the same time as the RDRF bit which

itself generates an interrupt. If the word currently being transferred causes both frame error

and overrun error, it is transferred and only the OR bit is set.

Bit 0 = PE Parity error.

This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by a

software sequence (a read to the status register followed by an access to the SCIDR data

0: no parity error

1: parity error

ST72361AR4-Auto Datasheet(PDF) 206 Page - STMicroelectronics

ST72361AR4-Auto Datasheet(HTML) 206 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL