ST72361AR4-Auto datasheet(210/279 Pages) STMICROELECTRONICS

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LINSCI serial communication interface (LIN master only)

ST72361xx-Auto

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Doc ID 12468 Rev 3

Bit 1 = CPHA Clock Phase.

This bit allows the user to select the phase of the clock output on the SCLK pin. It works in

conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure 92

and Figure 93)

0: SCLK clock line activated in middle of data bit.

1: SCLK clock line activated at beginning of data bit.

Bit 0 = LBCL Last bit clock pulse.

This bit allows the user to select whether the clock pulse associated with the last data bit

transmitted (MSB) has to be output on the SCLK pin.

0: the clock pulse of the last data bit is not output to the SCLK pin.

1: the clock pulse of the last data bit is output to the SCLK pin.

Note:

The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format selected

by the M bit in the SCICR1 register.

Note:

These 3 bits (CPOL, CPHA, LBCL) should not be written while the transmitter is enabled.

16.8.5

Data register (SCIDR)

Read/ write

Reset value: Undefined

Contains the received or transmitted data character, depending on whether it is read from or

written to.

The data register performs a double function (read and write) since it is composed of two

registers, one for transmission (TDR) and one for reception (RDR).

The TDR register provides the parallel interface between the internal bus and the output

shift register (see Figure 88).

The RDR register provides the parallel interface between the input shift register and the

internal bus (see Figure 88).

Table 76.

SCI clock on SCLK pin

Data format

M bit

LBCL bit

Number of clock pulses on SCLK

8 bit

9 bit

DR7

DR6

DR5

DR4

DR3

DR2

DR1

DR0

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