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ST72361AR4-Auto Datasheet(PDF) 211 Page - STMicroelectronics

Part # ST72361AR4-Auto
Description  Clock, reset and supply management
PDF  279 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72361AR4-Auto Datasheet(HTML) 211 Page - STMicroelectronics

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ST72361xx-Auto
LINSCI serial communication interface (LIN master only)
Doc ID 12468 Rev 3
211/279
16.8.6
Baud rate register (SCIBRR)
Read/ write
Reset value: 0000 0000 (00h)
Bits 7:6 = SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard clock division ranges:
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 and SCP0 bits define the total division applied to
the bus clock to yield the transmit rate clock in conventional baud rate generator mode.
Note:
This TR factor is used only when the ETPR fine tuning factor is equal to 00h; otherwise, TR
is replaced by the (TR*ETPR) dividing factor.
Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP1 and SCP0 bits define the total division applied to
the bus clock to yield the receive rate clock in conventional baud rate generator mode.
7
0
SCP1
SCP0
SCT2
SCT1
SCT0
SCR2
SCR1
SCR0
Table 77.
PR prescaler
PR prescaling factor
SCP1
SCP0
1
0
0
31
4
1
0
13
1
Table 78.
Transmitter rate divider
TR dividing factor
SCT2
SCT1
SCT0
1
0
0
0
21
4
1
0
81
16
1
0
0
32
1
64
1
0
128
1



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