ST72361AR4-Auto datasheet(209/279 Pages) STMICROELECTRONICS

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ST72361xx-Auto

LINSCI serial communication interface (LIN master only)

Doc ID 12468 Rev 3

209/279

Bit 0 = SBK Send break.

This bit set is used to send break characters. It is set and cleared by software.

0: no break character is transmitted

1: break characters are transmitted

Note:

If the SBK bit is set to “1” and then to “0”, the transmitter sends a BREAK word at the end of

the current word.

16.8.4

Control Register 3 (SCICR3)

Read/ write

Reset value: 0000 0000 (00h)

Bit 7 = Reserved, must be kept cleared.

Bit 6 = LINE LIN Mode Enable.

This bit is set and cleared by software.

0: LIN mode disabled

1: LIN master mode enabled

The LIN Master mode enables the capability to send LIN Synch Breaks (13 low bits) using

the SBK bit in the SCICR2 register.

In transmission, the LIN synch break low phase duration is shown as below:

Bits 5:4 = Reserved, forced by hardware to 0.

These bits are not used.

Bit 3 = CLKEN Clock Enable.

This bit allows the user to enable the SCLK pin.

0: SLK pin disabled

1: SLK pin enabled

Bit 2 = CPOL Clock Polarity.

This bit allows the user to select the polarity of the clock output on the SCLK pin. It works in

conjunction with the CPHA bit to produce the desired clock/data relationship (see Figure 92

and Figure 93).

0: steady low value on SCLK pin outside transmission window.

1: steady high value on SCLK pin outside transmission window.

LINE

CLKEN

CPOL

CPHA

LBCL

Table 75.

LIN sync break duration

LINE

Number of low bits sent during a LIN synch break

010

111

013

114

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