ST72361AR4-Auto datasheet(205/279 Pages) STMICROELECTRONICS

205 / 279 page

ST72361xx-Auto

LINSCI serial communication interface (LIN master only)

Doc ID 12468 Rev 3

205/279

Figure 93.

SCI data clock timing diagram (M = 1)

16.8

16.8.1

Status register (SCISR)

Read only

Reset value: 1100 0000 (C0h)

Bit 7 = TDRE Transmit data register empty.

This bit is set by hardware when the content of the TDR register has been transferred into

the shift register. An interrupt is generated if the TIE bit = 1 in the SCICR2 register. It is

cleared by a software sequence (an access to the SCISR register followed by a write to the

SCIDR register).

0: data is not transferred to the shift register

1: data is transferred to the shift register

Note:

Data is not be transferred to the shift register until the TDRE bit is cleared.

Bit 6 = TC Transmission complete.

This bit is set by hardware when transmission of a frame containing Data is complete. An

interrupt is generated if TCIE = 1 in the SCICR2 register. It is cleared by a software

sequence (an access to the SCISR register followed by a write to the SCIDR register).

0: transmission is not complete

1: transmission is complete

Note:

TC is not set after the transmission of a Preamble or a Break.

Bit 5 = RDRF Received data ready flag.

This bit is set by hardware when the content of the RDR register has been transferred to the

SCIDR register. An interrupt is generated if RIE = 1 in the SCICR2 register. It is cleared by a

Idle or next

M = 1 (9 data bits)

Clock (CPOL=0, CPHA=1)

Clock (CPOL=1, CPHA=0)

Clock (CPOL=1, CPHA=1)

Start

LSB

MSB Stop

* LBCL bit controls last data clock pulse

Start

Idle or preceding

transmission

Data

Stop

Clock (CPOL=0, CPHA=0)

transmission

TDRE

RDRF

IDLE

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