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ST72361AR4-Auto Datasheet(PDF) 238 Page - STMicroelectronics

Part # ST72361AR4-Auto
Description  Clock, reset and supply management
PDF  279 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72361AR4-Auto Datasheet(HTML) 238 Page - STMicroelectronics

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Electrical characteristics
ST72361xx-Auto
238/279
Doc ID 12468 Rev 3
19.8
EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
19.8.1
Functional EMS (electromagnetic susceptibility)
Based on a simple running application on the product (toggling two LEDs through I/O ports),
the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
●
ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the
device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2
standard.
●
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100pF capacitor, until a functional disturbance occurs. This test
conforms with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations:
The software flowchart must include the management of runaway conditions such as:
●
Corrupted program counter
●
Unexpected reset
●
Critical data corruption (control registers...)
Prequalification trials:
tRET
Data retention
TA =55°C
20
years
NRW
Write erase cycles
TA = 85°C
100
cycles
TPROG
TERASE
Programming or erasing
temperature range
-40
25
85
°C
1.
Data based on characterization results, not tested in production.
2.
VPP must be applied only during the programming or erasing operation and not permanently for reliability
reasons.
3.
Data based on simulation results, not tested in production.
4.
In Write / erase mode the IDD supply current consumption is the same as in Run mode (see Section 20.2.2)
Table 100.
Dual voltage HDFlash memory (continued)
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1)
Unit



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