ST72361AR4-Auto datasheet(245/279 Pages) STMICROELECTRONICS

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ST72361xx-Auto

Electrical characteristics

Doc ID 12468 Rev 3

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Figure 111. Typical VOH vs VDD

19.10

Control pin characteristics

19.10.1

Asynchronous RESET pin

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Vdd(V)

-45°C

25°C

130°C

345

Vdd(V)

-45°C

25°C

130°C

Table 107.

RESET pin characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Input low level voltage(1)

0.3 x VDD

VIH

Input high level voltage(1)

0.7 x VDD

Vhys

Schmitt trigger voltage

hysteresis(2)

VDD =5V

1.5

VOL

Output low level voltage(3)

VDD =5V

IIO = +5mA

0.68

0.95

IIO = +2mA

0.28

0.45

RON

Weak pull-up equivalent

resistor(4)

VIN  VSS



tw(RSTL)out Generated reset pulse duration

Internal reset source

µs

th(RSTL)in

External reset pulse hold time(5)

2.5

tg(RSTL)in

Filtered glitch duration(6)

200

Data based on characterization results, not tested in production.

Hysteresis voltage between Schmitt trigger switching levels.

The IIO current sunk must always respect the absolute maximum rating specified in Section 20.2.2: Current characteristics

and the sum of IIO (I/O ports and control pins) must not exceed IVSS.

To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on the

RESET pin with a duration below th(RSTL)in can be ignored.

The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy

environments.

Data guaranteed by design, not tested in production.

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