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ST72361AR4-Auto Datasheet(PDF) 246 Page - STMicroelectronics |
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ST72361AR4-Auto Datasheet(HTML) 246 Page - STMicroelectronics |
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246 / 279 page ![]() Electrical characteristics ST72361xx-Auto 246/279 Doc ID 12468 Rev 3 RESET circuit design recommendations The reset network protects the device against parasitic resets. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog). Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below the VIL max. level specified in Section 20.10.1: Asynchronous RESET pin. Otherwise the reset will not be taken into account internally. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure that the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value specified for IINJ(RESET) in Section 20.2.2: Current characteristics. RESET pin protection when LVD is disabled Figure 112. RESET pin protection when LVD is disabled RESET pin protection when LVD is enabled Figure 113. RESET pin protection when LVD is enabled Note: When the LVD is enabled, it is mandatory not to connect a pull-up resistor. A 10nF pull-down capacitor is recommended to filter noise on the reset line. In case a capacitive power supply is used, it is recommended to connect a 1 M pull-down resistor to the RESET pin to discharge any residual voltage induced by this capacitive power supply (this will add 5 µA to the power consumption of the MCU). 0.01µF EXTERNAL RESET CIRCUIT USER VDD 4.7k Required ST72XXX PULSE GENERATOR Filter RON VDD WATCHDOG INTERNAL RESET 0.01µF ST72XXX PULSE GENERATOR Filter RON VDD WATCHDOG LVD RESET INTERNAL RESET RESET EXTERNAL Recommended 1M Optional (see note ) |
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