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ST72361AR4-Auto Datasheet(PDF) 251 Page - STMicroelectronics

Part # ST72361AR4-Auto
Description  Clock, reset and supply management
PDF  279 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72361AR4-Auto Datasheet(HTML) 251 Page - STMicroelectronics

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ST72361xx-Auto
Electrical characteristics
Doc ID 12468 Rev 3
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Figure 116. SPI slave timing diagram with CPHA = 0
1.
Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD
2.
When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave
mode) has its alternate function capability released. In this case, the pin status depends on the I/O port
configuration.
Figure 117. SPI slave timing diagram with CPHA = 1
1.
Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD.
2.
When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave
mode) has its alternate function capability released. In this case, the pin status depends on the I/O port
configuration.
SS INPUT
CPHA = 0
MOSI INPUT
MISO OUTPUT
CPHA = 0
tc(SCK)
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
tv(SO)
ta(SO)
tsu(SI)
th(SI)
MSB OUT
MSB IN
BIT6 OUT
LSB IN
LSB OUT
See note 2
CPOL = 0
CPOL = 1
tsu(SS)
th(SS)
tdis(SO)
th(SO)
See
note 2
BIT1 IN
SS INPUT
CPHA = 1
MOSI INPUT
MISO OUTPUT
CPHA = 1
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
ta(SO)
tsu(SI)
th(SI)
MSB OUT
BIT6 OUT
LSB OUT
See
CPOL = 0
CPOL = 1
tsu(SS)
th(SS)
tdis(SO)
th(SO)
See
note 2
note 2
tc(SCK)
Hz
tv(SO)
MSB IN
LSB IN
BIT1 IN



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