ST72561AR7-Auto datasheet(239/324 Pages) STMICROELECTRONICS

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ST72561-Auto

beCAN controller (beCAN)

Doc ID 12370 Rev 8

239/324

This bit controls the transmission order when several mailboxes are pending at the same

time.

●

0: priority driven by the identifier of the message

●

1: priority driven by the request order (chronologically)

Bit 1 = SLEEP Sleep Mode Request

Read/set/clear

This bit is set by software to request the CAN hardware to enter the sleep mode. Sleep

mode will be entered as soon as the current CAN activity (transmission or reception of a

CAN frame) has been completed.

This bit is cleared by software to exit sleep mode.

This bit is cleared by hardware when the AWUM bit is set and a SOF bit is detected on the

CAN Rx signal.

Bit 0 = INRQ Initialization Request

Read/set/clear

The software clears this bit to switch the hardware into normal mode. Once 11 consecutive

recessive bits have been monitored on the Rx signal the CAN hardware is synchronized and

ready for transmission and reception. Hardware signals this event by clearing the INAK bit if

the CMSR register.

Software sets this bit to request the CAN hardware to enter initialization mode. Once

software has set the INRQ bit, the CAN hardware waits until the current CAN activity

(transmission or reception) is completed before entering the initialization mode. Hardware

signals this event by setting the INAK bit in the CMSR register.

CAN master status register (CMSR)

Reset value: 0000 0010 (02h)

Note:

To clear a bit of this register the software must write this bit with a one.

Bits 7:4 = reserved. Forced to 0 by hardware.

Bit 5 = REC Receive

Read

The CAN hardware is currently receiver.

Bit 4 = TRAN Transmit

Read

The CAN hardware is currently transmitter.

Bit 3 = WKUI Wake-Up Interrupt

Read/clear

This bit is set by hardware to signal that a SOF bit has been detected while the CAN

hardware was in sleep mode. Setting this bit generates a status change interrupt if the

WKUIE bit in the CIER register is set.

This bit is cleared by software.

Bit 2 = ERRI Error Interrupt

Read/clear

This bit is set by hardware when a bit of the CESR has been set on error detection and the

REC

TRAN

WKUI

ERRI

SLAK

INAK

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