ST72561AR7-Auto datasheet(235/324 Pages) STMICROELECTRONICS

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ST72561-Auto

beCAN controller (beCAN)

Doc ID 12370 Rev 8

235/324

We could simply wait for the end of the reception, but this could take a long time (200µs for a

100-bit frame at 500 kHz), so we also monitor the Rx pin of the microcontroller to minimize

the time the application may wait in the while loop.

We know the critical window is located at the end of the frame, 6+ CAN bit times after the

acknowledge bit (exactly six full bit times plus the time from the beginning of the bit to the

sample point). Those bits represent the acknowledge delimiter + the end of frame slot.

We know also that those 6+ bits are in recessive state on the bus, therefore if the CAN Rx

pin of the device is at ‘0’, (reflecting a CAN dominant state on the bus), this is early enough

to be sure we can release the FIFO before the critical time slot.

Therefore, if the device hardware pin Rx is at 0 and there is a reception on going, its

message will be transferred to the FIFO only 6+ CAN bit times later at the earliest (if the

dominant bit is the acknowledge) or later if the dominant bit is part of the message.

Compiled with Cosmic C compiler, the workaround generates the following assembly lines:

In the worst case configuration, if the CAN cell speed is set to the maximum baud rate, one

bit time is 8 CPU cycle. In this case the minimum time between the end of the acknowledge

and the critical period is 52 CPU cycles (48 for the 6 bit times + 4 for the (PROP SEG +

TSeg1). According to the previous code timing, we need less than 15 cycles from the time we

see the dominant state to the time we perform the FIFO release (one full loop + the actual

release) therefore the application will never release the FIFO at the critical time when this

workaround is implemented.

Timing analysis

●

Time spent in the workaround

Inside a CAN frame, the longest period that the Rx pin stays in recessive state is 5 bits. At

the end of the frame, the time between the acknowledge dominant bit and the end of

reception (signaled by REC bit status) is 8tCANbit, therefore the maximum time spent in the

workaround is: 8tCANbit+tloop+ttest+trelease in this case or 8tCANbit+25tCPU.

At low speed, this time could represent a long delay for the application, therefore it makes

sense to evaluate how frequently this delay occurs.

In order to reach the critical FMP = 2, the CAN node needs to receive two messages without

servicing them. Then in order to reach the critical window, the cell has to receive a third one

and the application has to release the mailbox at the same time, at the end of the reception.

In the application, messages are not processed only if either the interrupt are disabled or

higher level interrupts are being serviced.

Cycles

if ((CRFR & 0x03) == 0x02)

a, CRFR

and

a,#3

a,#2

jrne

_RELEASE

test: 10 cycles

while

((CMSR & 0x20) && (CDGR & 0x08)) { };

_WHILELOOP:

btjf

CMSR,#5,_RELEASE

btjt

CDGR,#3,_WHILELOOP

loop: 10 cycles

CRFR |= B_RFOM;

_RELEASE:

bset

CRFR,#5

release: 5 cycles

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