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ST72561AR7-Auto Datasheet(PDF) 234 Page - STMicroelectronics

Part # ST72561AR7-Auto
Description  Clock, reset and supply management
PDF  324 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72561AR7-Auto Datasheet(HTML) 234 Page - STMicroelectronics

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beCAN controller (beCAN)
ST72561-Auto
234/324
Doc ID 12370 Rev 8
Figure 109. FIFO corruption
Workaround
To implement the workaround, use the following sequence to release the CAN receive FIFO.
This sequence replaces any occurrence of
CRFR |= B_RFOM;
.
Figure 110. Workaround 1
Explanation of workaround 1
First, we need to make sure no interrupt can occur between the test and the release of the
FIFO to avoid any added delay.
The workaround checks if the first two FIFO levels are already full (FMP = 2) as the problem
happens only in this case.
If FMP
≠ 2 we release the FIFO immediately, if FMP = 2, we monitor the reception status of
the cell.
The reception status is available in the CMSR register bit 5 (REC bit).
Note:
The REC bit was called RX in older versions of the datasheet.
●
If the cell is not receiving, then REC bit in CMSR is at 0, the software can release the
FIFO immediately: there is no risk.
●
If the cell is receiving, it is important to make sure the release of the mailbox will not
happen at the time when the received message is loaded into the FIFO.
Initial State
*v
* pointer to next receive location
v pointer to next message to be released
---
When the FIFO is empty, v and * point to the same location
FIFO
Receive Message A
*
v
A- -
Receive Message B
AB -
*
v
Receive Message C
ABC
*
v
* does not move because FIFO is full (normal operation)
Release Message A
ABC
v
*
Release Message B
DB C
and Receive Message D
*
v
DB C
*
Normal operation
* Does not move, pointer corruption
Receive Message E
EBC
Release Message C
EBC
*
v
Release Message E
EBC
*
v
C released
* v
Release Message B
EBC
* v
* and v are not pointing to the same message
D is overwritten by E
FMP
0
1
2
3
2
2
3
2
1
0
the FIFO is empty
v
E released instead of B
if ((CRFR & 0x03) == 0x02)
while
((CMSR & 0x20) && (CDGR & 0x08))
{ };
CRFR |= B_RFOM;



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