ST72561AR7-Auto datasheet(243/324 Pages) STMICROELECTRONICS

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ST72561-Auto

beCAN controller (beCAN)

Doc ID 12370 Rev 8

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Bit 7 = WKUIE Wake-Up Interrupt Enable

0: no interrupt when WKUI is set.

1: interrupt generated when WKUI bit is set.

Bits 6:4 = reserved. Forced to 0 by hardware.

Bit 3 = FOVIE FIFO Overrun Interrupt Enable\

0: no interrupt when FOVR bit is set.

1: interrupt generated when FOVR bit is set.

Bit 2 = FFIE FIFO Full Interrupt Enable

0: no interrupt when FULL bit is set.

1: interrupt generated when FULL bit is set.

Bit 1 = FMPIE FIFO Message Pending Interrupt Enable

0: no interrupt on FMP[1:0] bits transition from 00b to 01b.

1: interrupt generated on FMP[1:0] bits transition from 00b to 01b.

Bit 0 = TMEIE Transmit Mailbox Empty Interrupt Enable

0: no interrupt when RQCPx bit is set.

1: interrupt generated when RQCPx bit is set.

CAN error status register (CESR)

Read/ write

Reset value: 0000 0000 (00h)

Bit 7 = reserved. Forced to 0 by hardware.

Bits 6:4 = LEC[2:0] Last Error Code

Read/ set/ clear

This field holds a code which indicates the type of the last error detected on the CAN bus. If

a message has been transferred (reception or transmission) without error, this field will be

cleared to ‘0’. The code 7 is unused and may be written by the CPU to check for update

LEC2

LEC1

LEC0

BOFF

EPVF

EWGF

Table 85.

LEC error types

Code

Error type

0No Error

Stuff Error

Form Error

Acknowledgment Error

Bit recessive Error

Bit dominant Error

CRC Error

Set by software

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