STM8S105C4 datasheet(61/121 Pages) STMICROELECTRONICS

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STM8S105x4/6

Electrical characteristics

Low power mode wakeup times

Total current consumption and timing in forced reset state

Current consumption of on-chip peripherals

Subject to general operating conditions for VDD and TA.

Table 28. Wakeup times

Symbol

Parameter

Conditions

Typ

Max(1)

Unit

tWU(WFI)

Wakeup time from wait

mode to run mode(2)

0 to 16 MHz

See note(3)

µs

tWU(WFI)

Wakeup time from run

mode(2)

fCPU= fMASTER= 16 MHz

0.56

tWU(AH)

Wakeup time active halt

mode to run mode(2)

MVR voltage

regulator on(4)

Flash in

operating

mode(5)

HSI (after

wakeup)

1(6)

2(6)

tWU(AH)

Wakeup time active halt

mode to run mode(2)

MVR voltage

regulator off(4)

Flash in

operating

mode(5)

HSI (after

wakeup)

3(6)

tWU(AH)

Wakeup time active halt

mode to run mode(2)

MVR voltage

regulator off(4)

Flash in

operating

mode(5)

HSI (after

wakeup)

48(6)

tWU(AH)

Wakeup time active halt

mode to run mode(2)

MVR voltage

regulator off(4)

Flash in

power-down

mode(5)

HSI (after

wakeup)

50(6)

tWU(H)

Wakeup time from halt

mode to run mode(2)

Flash in operating mode(5)

tWU(H)

Wakeup time from halt

mode to run mode(2)

Flash in power-down mode(5)

Data based on characterization results, not tested in production.

2. Measured from interrupt event to interrupt vector fetch

3. tWU(WFI) = 2 x 1/fmaster + 67 x 1/fCPU

4. Configured by the REGAH bit in the CLK_ICKR register.

5. Configured by the AHALT bit in the FLASH_CR1 register.

6. Plus 1 LSI clock depending on synchronization.

Table 29. Total current consumption and timing in forced reset state

Symbol

Parameter

Conditions

Typ

Max(1)

1. Data guaranteed by design, not tested in production.

Unit

IDD(R)

Supply current in reset

state(2)

Characterized with all I/Os tied to VSS.

VDD = 5 V

500

µA

VDD = 3.3 V

400

tRESETBL

Reset pin release to

vector fetch

150

µs

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