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STM32F383RC Datasheet(PDF) 83 Page - STMicroelectronics

Part # STM32F383RC
Description  Reset and power management
PDF  125 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F383RC Datasheet(HTML) 83 Page - STMicroelectronics

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STM32F383xx
Electrical characteristics
109
Note:
I/O pins are powered from VDD voltage except pins which can be used as SDADC inputs:
- The PB10 and PE7 to PE15 I/O pins are powered from VDDSD12.
- PB14 to PB15 and PD8 to PD15 I/O pins are powered from VDDSD3. All I/O pin ground is
internally connected to VSS.
VDD mentioned in the Table 49 represents power voltage for a given I/O pin (VDD or
VDDSD12 or VDDSD3).
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology parameters. The coverage of
these requirements is shown in Figure 17 for standard I/Os, and in Figure 18 for 5 V
tolerant I/Os.
Figure 17. TC and TTa I/O input characteristics
Figure 18. Five volt tolerant (FT and FTf) I/O input characteristics
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ± 8 mA, and sink or
source up to ± 20 mA (with a relaxed VOL/VOH).
MS31122V2
VDD (V)
VIHmin
VILmax
VIL/VIH (V)
1.65
1.95
CMOS standard requirements
VIHmin = 0.7VDD
VILmax
= 0.3V
DD
+0.07
1.8
CMOS standard requirements VILmax = 0.3VDD
VIHmin
= 0.445V
DD
+0.398
Area not determined
0.5
0.7
0.9
1.1
1.3
Tested in production
Tested in production
Based
on design
simulations
Based
on design
simulations
MS31123V2
VDD (V)
VIHmin
VILmax
VIL/VIH (V)
1.65
1.95
CMOS standard requirements
V
IHmin = 0.7VDD
VILmax
= 0.475V
DD -
0.2
1.8
CMOS standard requirements VILmax = 0.3VDD
VIHmin
= 0.5V
DD
+0.2
Area not determined
0.5
0.7
0.9
1.1
1.3
Tested in production
Tested in production
Based
on design
simulations
Based
on design
simulations



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